1. Field of the Invention
The present invention relates to integrated circuit devices, and more specifically to an output driver circuit for integrated circuit devices.
2. Background Art
An integrated circuit (IC) is typically a small chip of semiconductor material upon which active and/or passive components have been fabricated and interconnected to form a functioning circuit. ICs are generally encapsulated with signal, power supply, and control pads (pins or terminals) accessible for connection to external electronic circuitry. Programmable logic devices (PLDs) are one type of IC in which the active/passive components are user-programmable to implement a desired logic function. Typically, input signals transmitted to a PLD via selected input or Input/output (I/O) pads are processed by the programmed array of active and/or passive components, and the processed signals are then applied to selected output or I/O pads using an output driver circuit. The output driver circuit raises (pulls up) or lowers (pulls down) a voltage level of the output or I/O pad in response to the processed signals generated by the programmed array, thereby providing logic "1" and "0" signals which are transmitted to the external circuitry connected to the output or I/O pad.
FIG. 1 is a circuit diagram showing a known output driver circuit 100 used, for example, in some of the PLDs produced by Xilinx, Inc. of San Jose, Calif. Output driver circuit 100 is controlled by a pull-up signal source 110 and a pull-down signal source 120 which generate non-overlapping signals. In a pull-up mode, the output driver circuit 100 connects an output (or I/O) pad 101 to a voltage source V.sub.DD through P-channel pull-up transistor 115, which has a channel width-to-length ratio of 400/0.5. Conversely, in a pull-down mode, the output driver 100 connects the output pad 101 to ground through a pull-down circuit 130, which is programmable to operate in either a "normal" operating mode or in a "soft-edge" operating mode.
The pull-down circuit 130 includes a first N-channel pull-down transistor 131 and a second N-channel pull-down transistor 132, both being connected between the output pad 101 and ground. The channel width-to length ratios for the first N-channel transistor 131 is 360/0.5, and that of the second N-channel transistor 132 is 108/0.5. The first pull-down transistor 131 has a gate connected directly to the pull-down signal source 120, and therefore conducts each time the pull-down signal source 120 generates a high signal. Signals applied to the gate of the second pull-down transistor 132 are controlled by memory circuit 133 whose output is connected to the gates of a first transmission gate 134 and a second transmission gate 135 using inverter 136. The first transmission gate 134 is connected between the pull-down signal source 120 and the gate of the second pass transistor 132. The second transmission gate 135 is connected to a third transmission gate 137, which in turn is connected to the output pad 101 through a resistor R1. The third transmission gate 137 is controlled by the pull-down signal source 120 and output of inverter 138, which is also connected to the gate of a third N-channel transistor 139. The third N-channel transistor 139 is connected between an output of the third transmission gate 137 and ground.
The output driver circuit 100 is typically programmed to operate in the "normal" operating mode when a user is more concerned about operating speed than with noise in the output signal. In the "normal" operating mode of the known output driver circuit 100, the memory circuit 133 is programmed to turn on first transmission gate 134 and to turn off second transmission gate 135. With the first transmission gate 134 turned on, the first and second pull-down transistors (131 and 132) are controlled by the pull-down signal source 120. Specifically, a high signal generated by the pull-down signal source 120 saturates both the first and second N-channel transistors (131 and 132), thereby allowing the voltage level on the output pad 101 to discharge at a relatively fast rate. However, in some situations this relatively fast discharge rate can result in a ground bounce (shifting of the voltage at ground terminals of the IC chip) which can generate improper output signals. For example, when too many output pads of a PLD are switched from V.sub.DD to ground simultaneously, the resulting load can create significant ground bounce.
To avoid ground bounce (when this is a problem), a user may selectively operate the output driver circuit 100 in the "soft-edge" operation mode. In this mode, the memory circuit 133 is loaded with a logic 1 value to turn off the first transmission gate 134 and to turn on the second transmission gate 135. With the second transmission gate 135 turned on, a portion of the voltage level on output pad 101 is fed back through resistor R1, third transmission gate 137 and second transmission gate 135 to the gate of second pull-down transistor 132. The third transmission gate 137 is controlled by the pull-down signal source using inverter 138 to turn on transistor 139.
When the signal generated by the pull-down signal source 120 is low, the first N-channel transistor 131 is turned off. In addition, this low signal turns off third transmission gate 137 and turns on the third N-channel transistor 139 (through the inverter 138). With the third N-channel transistor 139 turned on, the gate of the second N-channel transistor 132 is connected to ground, thereby turning off the second N-channel transistor 132. Thus, when source 120 is low, neither of transistors 131 or 132 pull down output pad 101.
When the signal generated by the pull-down signal source 120 switches from low to high, this high signal turns on the first N-channel transistor 131. In addition, this high signal turns on the third transmission gate 137 and turns off the third N-channel transistor 139, thereby effectively connecting the output pad 101 to the gate of second N-channel transistor 132. Because the voltage level of the output pad 101 is V.sub.DD at this time, the second N-channel transistor 132 is also turned on. Therefore, at this initial point following the transition of the pull-down signal 120 from low to high, the discharge rate of the output pad 101 is substantially at the same relatively fast discharge rate achieved in the "normal" operating mode. However, as the output pad 101 discharges, the voltage level fed back to the gate of the second N-channel transistor 132 is correspondingly reduced, thereby gradually turning off the second N-channel transistor 132. This attempts to produce the desired "soft-edge" effect by reducing the discharge rate of the output pad 101 as the voltage level of the output pad 101 approaches the ground level. A structure similar to FIG. 1 is also described by Pierce, et al. in U.S. Pat. No. 5,319,252, commonly assigned.
A problem with the known output driver circuit 100 occurs because the second N-channel transistor 132 turns off before the voltage level of the output pad 101 reaches the ground potential, and remains turned off after the output pad 101 is at the ground potential. In particular, the second N-channel transistor 132 turns off during discharge when the voltage level of the output pad 101 falls below the threshold voltage V.sub.Th of the second N-channel transistor 132, and remains turned off thereafter. Because the second N-channel transistor 132 is off when the output voltage is at the ground potential, the channel width-to-length ratio of the first N-channel transistor 131 is necessarily larger (as mentioned above, approximately 3 times larger) than that of the second N-channel transistor 132 in order to meet D.C. output specifications. This difference creates sudden changes in capacitive load on the gate of the first N-channel transistor 131 when the first transmission gate 134 turns off, thereby increasing the discharge rate through the first N-channel transistor 131. This sudden increase in discharge rate can result in ground bounce.